Wa_audience: "emtaudience:business/btssbusinesstechnologysolutionspecialist/developer/fpgaengineer", Multi Channel DMA Intel FPGA IP for PCI Express : IP Core ", Wa_emtsubject: "emtsubject:design/fpgadesign/signalintegrity", Wa_primarycontenttagging: "primarycontenttagging:intelfpgas/intelprogrammabledevices/intelstratix/intelstratix10fpgasandsocfpgas,primarycontenttagging:intelfpgas/intelfpgaintellectualproperty/interfaceprotocols,primarycontenttagging:intelfpgas/intelprogrammabledevices/intelagilexfpgasandsocfpgas,primarycontenttagging:intelfpgas/intelprogrammabledevices", Wa_emtcontenttype: "emtcontenttype:designanddevelopmentreference/releasenotes", You can implement multiple PFs/VFs: Up to 8 PFs in P-Tile and 4 PFs in H-Tile.Īdded support for MCDMA AVST 1 port interface.ĪVST 1 port interface enables you to implement multiple channels of H2D/D2H DMA. You can write to/read from the downstream Endpoint configuration space registers using the Config Slave interface.Īdded support for user MSI-X in MCDMA mode.Īdded support for user FLR in MCDMA mode.Įndpoint user logic can be reset by the Function Level Reset. You can implement a user mode that best suits your application needs based on the port usage (Root Port / Endpoint).Īdded support for Configuration Slave interface for Root Port mode. You can implement Gen3 x16/x8 link in Intel Stratix 10 GX and MX device families.Īdded support for various user modes: Multi channel DMA (EP), Bursting Master (RP, EP), Bursting Slave (RP, EP), BAM-BAS (RP, EP) and BAM-MCDMA (EP). You can implement up to Gen4 x16 link in Intel® Stratix® 10 DX and Intel® Agilex™ FPGA device families.Īdded support for H-Tile Gen3 x8 and Root Port mode. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core 2021.07.19 Intel® Quartus® Prime VersionĪdded support for P-Tile Gen4/Gen3 x16 (Root Port, Endpoint) and x8 (Endpoint).
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